使用PrimePower

PrimePower是Gate Level Power Estimation的工具

使用的程序如下:
1. 先合成出gate level的net list
2. 輸出 netlist 以及sdf
3. 跑gate level simulation在 Test Bench先要加入以下兩行
$sdf_annotate("aaa.sdf", U_aaa");
$dumpfile("aaa.vcd")
4. 會得到aaa.vcd, 然後再執行PrimePower


以下指令:
set search_path {. /aaa/bbb} // /aaa/bbb是Cell Lib的路徑
set link_lib {* xxx.db} // xxx.db是所使用的Cell Lib
set target_lib {* xxx.db}
read_verilog aaa.v // aaa.v是合成出來的gate level netlist
current_design aaa // aaa是 Top Module
read_vcd -strip_path tb_aaa/U_aaa aaa.vcd //tb_aaa/U_aaa 是 Test Bench裡面Top Module
calculate_power -waveform //註: -waveform才會有Peak Power的結果
report_power

使用PowerCompiler

1. 在Verilog Test Bench 加入
initial begin
$dumpfile("xxx.vcd");
$dumpvars;
end

2. 將vcd格式轉為saif格式 (Linux 指令)
vcd2saif -i xxx.vcd -o xxx.saif

3. 將Saif讀進來 (DC Shell)
read_saif -input xxx.saif -instance tb_core/U_CORE

Verilog File I/O System Task

integer $fopen(file_name, mode)
file_name: 要開啟檔案的名稱
mode : "r" for read "w" for write
Return : 會回傳一個數字表示 file descriptor

integer $fread(mem, fd, start, num)
mem : 資料要寫入的地方
fd : file descriptorstart : 資料要從 mem 的第幾筆開始寫
num : 要讀幾筆 (一筆的寬度是由mem的宣告決定)
return : 會回傳到底讀了多少 byte

integer $fseek(fd, nb, mode)
fd : file descriptor
nb : number of byte
mode :
0: seek from begin
1: seek from current
2: seek from end

integer $fscanf(fd, format, args...)
fd: file descriptor
format: format
args: 參數
Returns:回傳讀了多少參數

$fdisplay(fd, format, args...)
fd: file descriptor
format: format

How To: SystemC

1. Dowload SystemC Source Code <http://www.systemc.org/>
2. Make Library using VC
3. SystemC Tutorial <http://www.doulos.com/knowhow/systemc/tutorial/>
4. Turn on VC "/vmg" option
Project Property >> Gneral >> C/C++ >> Commaind Line >> Other

Extensible Firmware Interface(EFI)

The EFI specification defines a new model for the interface between operating systems and platform firmware. The interface consists of data tables that contain platform-related information, plus boot and runtime service calls that are available to the operating system and its loader. Together, these provide a standard environment for booting an operating system and running pre-boot applications.

Free Programer's Resource

http://www.thefreecountry.com

Assembler/Compiler

ELF
"Tool Interface Standards (TIS) Executable and Linkable Format Specificaton" Version 1.2

DWARF format

RapidIO

主要用在嵌入式環境~
有Parallel以及Serial的介面~
http://www.rapidio.org/home

PCB Clock Tree

Zero Delay Buffer + Clock Driver
connect feedback of Clock Driver to Zero Dealy Buffer

[Book] Processor Design

1. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools
2. Modern Processor Design
3. HyperTranport System Architecture

虛擬技術(Virtualization Technology)

Intel Virtualization Technology
AMD Pacifica
讓一顆處理器"同時"執行多個系統, 不知道會不會起來,
感覺好像是執行一個系統的速度已經到一定的瓶頸了
而故意找事情做~

HyperTransport

目前AMD處理器採用的Bus Protocol
有書專門介紹 HyperTranport System Architecture

P4's quad-pumped FSB?

DDR is send data at rising edge and falling edge.
quad-pumped is send data twice at rising edge and falling edge.
rising edge: (0V->0.7V) and (0.7V->1.5V)
falling edge: (1.5V->0.7V) and (0.7V->0V)

DRAM介紹

SDRAM
最基本的DRAM,每個Clock Cycle傳輸1筆資料
DDR
每個Clock Cycle傳輸2筆資料(正緣,負緣)
DDR-II
每個Clock Cycle傳輸2筆資料(正緣,負緣), 內部跑的Clcok是外部的一半
QDR
每個Clock Cycle傳輸2筆資料(正緣,負緣), 讀跟寫分開,所以是4倍
QDR-II
每個Clock Cycle傳輸2筆資料(正緣,負緣), 讀跟寫分開,所以是4倍,與QDR在內部架構有些許差異
RLDRAM
Low Latency DRAM

FSB

Front Side Bus
CPU與晶片組溝通的介面
並沒有一定的規範, Intel/AMD兩家的訊號就不同
傳輸速度會比後面介面(Memory/PCIe)的速度快或相等

[DSP] VoIP

DSP的應用之一
設計時可以針對各種VoIP 聲音壓縮標準作最佳化