Embedded RTOS

1. uC/OS-II
非常迷你的OS, 從8051, PIC到32-bit CPU都有Port, 要自己Porting自己CPU也很快上手
除了基本的Kernel及TCP/IP有Open Source, 其它例如Filesystem都要額外付錢,
有四種License方式Single Product, Product Line, Per CPU-Type, Site

2. RTEMS
RTOS for Multiprocessor Systems, 支援許多open API Stanard: POISIX, VEMbus, TCP/IP including BSD Socket, uITRON.
在網路方面大部份的Service都有, Filesystem支援FAT, TFTP, NFS
但是支援的CPU種類較少, 而且偏向是比較高階的CPU

3. DSPnano
前身是Unison, 對DSP最最佳化處理, Eclips-based的開發環境

Chip Debug Industry Related

http://www.us.design-reuse.com/exit/?url=http%3A%2F%2Fwww.embedded.com%2Fshared%2FprintableArticle.jhtml%3FarticleID%3D201000620

1) Nexus (IEEE 5001) Forum, which is focused on high performance trace related interfaces based on the IEEE 5001 (Nexus) standard;
2) MIPI Alliance Test and Debug working group whic is addressing a range of debug interface efforts;
3) IJTAG (P1687) , which is a working group looking at JTAG extensions
4) Multicore Association (MCA) which is looking at integrated set of Debug and Communication APIs for Multicore architectures.
5) AJTAG (P1149.7) which is looking at 2 wire JTAG architectures
6) SPIRIT Consortium has a Debug working group looking at debug register description within the SPIRIT IP-XACT frameworks.

Debug Audio

http://www.insidedsp.com/tabid/64/articleType/ArticleView/articleId/207/Tips-and-Tricks-for-Debugging-Audio.aspx

Annotation of heterogeneous designs in OrCAD Capture

1. 在Part Property新增一Column "Group"
2. 將同一Part的Package的Group設為一樣
3. 在Annotate的Physical Packing 加入"{Group}"

SystemC Module Constructor (SC_HAS_PROCESS)

典型的SystemC Module 寫法:

SC_MODULE(module_test) {
public:
   SC_CTOR(module_test) {}
};

但是如果Constructor要傳入不同變數的時後必須換另一種寫法

class module_test: public sc_module {
public:
    module_test(sc_module_name nm, ....): sc_module(nm) {....}
};

但是在這這種情況下, 如果module裡面要宣告Process
例如SC_METHOD, SC_THREAD, SC_CTHREAD 就會有問題,
因為Process 會用到 SC_CTOR這個macro所定義到的一些東西
所以要用下面這種寫法

class module_test: public sc_module {
public:
    SC_HAS_PROCESS(module_test)
    module_test(sc_module_name nm, ....): sc_module(nm)
    {
        SC_CTHREAD(....);
    }
};

SystemC x86_64

1. 2.1版的不支援, 請用2.2beta版
2. 將configure裡面的LD_FLAGS改為LDFLAGS

參考文章: http://panoramis.free.fr/search.systemc.org/?pdoc=systemc/64bits

使用PrimePower

PrimePower是Gate Level Power Estimation的工具

使用的程序如下:
1. 先合成出gate level的net list
2. 輸出 netlist 以及sdf
3. 跑gate level simulation在 Test Bench先要加入以下兩行
$sdf_annotate("aaa.sdf", U_aaa");
$dumpfile("aaa.vcd")
4. 會得到aaa.vcd, 然後再執行PrimePower


以下指令:
set search_path {. /aaa/bbb} // /aaa/bbb是Cell Lib的路徑
set link_lib {* xxx.db} // xxx.db是所使用的Cell Lib
set target_lib {* xxx.db}
read_verilog aaa.v // aaa.v是合成出來的gate level netlist
current_design aaa // aaa是 Top Module
read_vcd -strip_path tb_aaa/U_aaa aaa.vcd //tb_aaa/U_aaa 是 Test Bench裡面Top Module
calculate_power -waveform //註: -waveform才會有Peak Power的結果
report_power

使用PowerCompiler

1. 在Verilog Test Bench 加入
initial begin
$dumpfile("xxx.vcd");
$dumpvars;
end

2. 將vcd格式轉為saif格式 (Linux 指令)
vcd2saif -i xxx.vcd -o xxx.saif

3. 將Saif讀進來 (DC Shell)
read_saif -input xxx.saif -instance tb_core/U_CORE

Verilog File I/O System Task

integer $fopen(file_name, mode)
file_name: 要開啟檔案的名稱
mode : "r" for read "w" for write
Return : 會回傳一個數字表示 file descriptor

integer $fread(mem, fd, start, num)
mem : 資料要寫入的地方
fd : file descriptorstart : 資料要從 mem 的第幾筆開始寫
num : 要讀幾筆 (一筆的寬度是由mem的宣告決定)
return : 會回傳到底讀了多少 byte

integer $fseek(fd, nb, mode)
fd : file descriptor
nb : number of byte
mode :
0: seek from begin
1: seek from current
2: seek from end

integer $fscanf(fd, format, args...)
fd: file descriptor
format: format
args: 參數
Returns:回傳讀了多少參數

$fdisplay(fd, format, args...)
fd: file descriptor
format: format

How To: SystemC

1. Dowload SystemC Source Code <http://www.systemc.org/>
2. Make Library using VC
3. SystemC Tutorial <http://www.doulos.com/knowhow/systemc/tutorial/>
4. Turn on VC "/vmg" option
Project Property >> Gneral >> C/C++ >> Commaind Line >> Other

Extensible Firmware Interface(EFI)

The EFI specification defines a new model for the interface between operating systems and platform firmware. The interface consists of data tables that contain platform-related information, plus boot and runtime service calls that are available to the operating system and its loader. Together, these provide a standard environment for booting an operating system and running pre-boot applications.

Free Programer's Resource

http://www.thefreecountry.com

Assembler/Compiler

ELF
"Tool Interface Standards (TIS) Executable and Linkable Format Specificaton" Version 1.2

DWARF format

RapidIO

主要用在嵌入式環境~
有Parallel以及Serial的介面~
http://www.rapidio.org/home

PCB Clock Tree

Zero Delay Buffer + Clock Driver
connect feedback of Clock Driver to Zero Dealy Buffer

[Book] Processor Design

1. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools
2. Modern Processor Design
3. HyperTranport System Architecture

虛擬技術(Virtualization Technology)

Intel Virtualization Technology
AMD Pacifica
讓一顆處理器"同時"執行多個系統, 不知道會不會起來,
感覺好像是執行一個系統的速度已經到一定的瓶頸了
而故意找事情做~

HyperTransport

目前AMD處理器採用的Bus Protocol
有書專門介紹 HyperTranport System Architecture

P4's quad-pumped FSB?

DDR is send data at rising edge and falling edge.
quad-pumped is send data twice at rising edge and falling edge.
rising edge: (0V->0.7V) and (0.7V->1.5V)
falling edge: (1.5V->0.7V) and (0.7V->0V)

DRAM介紹

SDRAM
最基本的DRAM,每個Clock Cycle傳輸1筆資料
DDR
每個Clock Cycle傳輸2筆資料(正緣,負緣)
DDR-II
每個Clock Cycle傳輸2筆資料(正緣,負緣), 內部跑的Clcok是外部的一半
QDR
每個Clock Cycle傳輸2筆資料(正緣,負緣), 讀跟寫分開,所以是4倍
QDR-II
每個Clock Cycle傳輸2筆資料(正緣,負緣), 讀跟寫分開,所以是4倍,與QDR在內部架構有些許差異
RLDRAM
Low Latency DRAM